A typical programmable logic device (PLD) uses conventional N-type metal oxide semiconductor (NMOS) or complementary metal oxide semiconductor (CMOS) transistors. Control voltages within the PLD cause the NMOS or CMOS transistors to turn on or off, thus providing programmable circuitry within the PLD.
Like many other electronic devices, supply voltages for typical PLDs have tended to decrease. The decreased supply voltages often accompany higher speeds of operation and lower power dissipation. The trend towards decreased supply voltages, however, has tended to make the operation of pass transistors and, therefore, the operation of the overall PLD, less reliable.
As the supply voltage decreases, transistors within the PLD (for example, NMOS pass transistors) have increasing difficulty in transmitting a logic 1 (i.e., logic high) level. With sufficiently small power-supply voltages, the pass transistors fail to reliably transmit a logic 1 level, thus causing circuit failure. This problem becomes even more acute in situations where the PLD includes the cascade of several transistors, such as several pass transistors in series. A need therefore exists for transistors that can reliably transmit both binary logic levels (i.e., both logic 0 and logic 1 levels) in PLDs, even with relatively small power-supply voltages.
This invention contemplates PLDs that include silicon-on-insulator (SOI) metal oxide semiconductor (MOS) transistors. In one embodiment, a PLD according to the invention includes programmable electronic circuitry that includes a plurality of SOI transistors. The programmable electronic circuitry allows programming the functionality of the PLD. More particularly, the programmable electronic circuitry includes: (a) at least one dynamic threshold metal oxide semiconductor (DTMOS) transistor, (b) at least one fully depleted metal oxide semiconductor (FDMOS) transistor, (c) at least one partially depleted metal oxide semiconductor (PDMOS) transistor, or (d) at least one double-gate metal oxide semiconductor transistor, or a combination thereof.
In another embodiment, a PLD according to the invention includes programmable electronic circuitry that includes a plurality of double-gate MOS transistors. The programmable electronic circuitry allows programming the functionality of the PLD. More particularly, the programmable electronic circuitry may include a programmable interconnect, a pass transistor, a look-up table circuit, and a multi-input logic circuit. The programmable interconnect couples to the pass transistor, the look-up table circuit, and the multi-input logic circuit.
In a third embodiment, a PLD according to the invention includes programmable interconnect circuitry, an SOI pass transistor, and a look-up table circuit. The programmable interconnect circuitry provides configurable interconnections within the PLD, and includes a first SOI transistor. The SOI pass transistor and the look-up table circuit both couple to the programmable interconnect circuitry. The look-up table circuit includes a second SOI transistor.
In another embodiment according to the invention, a PLD includes programmable interconnect circuitry that has at least one dynamic threshold metal oxide semiconductor (DTMOS) SOI transistor. The programmable interconnect circuitry couples together various electronic circuitry within the PLD. The PLD also includes at least one DTMOS pass transistor that couples to the programmable interconnect circuitry. Furthermore, the PLD includes at least one look-up table circuit, having at least one DTMOS SOI transistor, that also couples to the programmable interconnect circuitry.
In a fifth embodiment, a data-processing system according to the invention includes a PLD. The PLD includes programmable electronic circuitry, which has a plurality of MOS transistors. The data-processing system also includes at least one peripheral device coupled to the PLD. The plurality of MOS transistors includes at least one SOI transistor.
More particularly, the PLD may include at least one programmable interconnect, at least one pass transistor, at least one look-up table circuit, and at least one multi-input logic circuit. Each of the at least one programmable interconnect, the at least one pass transistor, the at least one look-up table circuit, and the at least one multi-input logic circuit includes one or more of: (a) a dynamic threshold metal oxide semiconductor (DTMOS) transistor, (b) a fully depleted metal oxide semiconductor (FDMOS) transistor, (c) a partially depleted metal oxide semiconductor (PDMOS) transistor, or (d) a double-gate metal oxide semiconductor transistor, or a combination thereof.
Another aspect of the invention relates to methods of processing data using a PLD. In one embodiment, the method includes receiving and processing input data in programmable electronic circuitry included within the PLD. The programmable electronic circuitry includes at least one SOI transistor.
More particularly, receiving and processing the input data according to the method includes: (a) using at least one programmable interconnect within the programmable interconnect circuitry; (b) using at least one pass transistor coupled to the at least one programmable interconnect circuitry; (c) using at least one look-up table circuit coupled to the at least one programmable interconnect; and (d) using at least one multi-input logic circuit coupled to the at least one programmable interconnect. Each of the at least one programmable interconnect, the at least one pass transistor, the at least one look-up table circuit, and the at least one multi-input logic circuit includes one or more of (a) a dynamic threshold metal oxide semiconductor (DTMOS) transistor, (b) a fully depleted metal oxide semiconductor (FDMOS) transistor, (c) a partially depleted metal oxide semiconductor (PDMOS) transistor, or (d) a double-gate metal oxide semiconductor transistor, or a combination thereof.